Implementación hardware de la función Hash SHA3-256 usando una arquitectura Pipeline

Nataly Nieto Ramírez; Rubén Darío Nieto Londoño

Hardware implementation of SHA3-256 Hash function using a Pipeline architecture

Authors

Nataly Nieto Ramírez Escuela de Ingeniería Eléctrica y Electrónica. Universidad del Valle, Cali, Colombia
Rubén Darío Nieto Londoño Escuela de Ingeniería Eléctrica y Electrónica. Universidad del Valle, Cali, Colombia

Keywords:

Cryptographic hash function, FPGA, hardware implementation, Keccak, pineline, SHA-3

Abstract

Hash functions are fundamental for computer security applications. This paper presents a two-stage pipelined architecture for SHA3-256, implemented in a Xilinx Virtex-5 FPGA, achieving a throughput of 27.98 Gbps.

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Published

2024-10-28

How to Cite

[1]

N. Nieto Ramírez and R. D. Nieto Londoño, “Hardware implementation of SHA3-256 Hash function using a Pipeline architecture”, Ingeniare, Rev. chil. ing., vol. 27, no. 1, Oct. 2024.

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Issue

Vol. 27 No. 1 (2019): Volumen 27 Issue 1

Section

Articulos

License

This work is licensed under a Creative Commons Attribution 4.0 International License.

Authors retain copyright of their work and grant the journal the right of first publication under the Creative Commons CC-BY Attribution License, which permits unrestricted use, distribution, and reproduction provided the original authorship and the journal’s first publication are acknowledged.