Four stage pipeline quaternary processor

Abstract

The scale of integration of processors has increased in recent decades, bringing new challenges, and chip area has become crucial. This work proposes the design of a four-stage pipelined quaternary processor (eCPU) with sixteen instructions, handling data and control hazards using hybrid (static and dynamic) techniques to demonstrate its functionality with respect to design specifications. The eCPU was designed using VHDL in Quartus® and simulated in ModelSim® to validate its behavior. Simulations were performed by running programs written in quaternary assembly language, supported by a two-phase compiler written in Java.